Embodiments of the present invention relate to a semiconductor memory device, and more specifically to a semiconductor memory device for preventing excessive application of a specific stress item during a test operation and a test method thereof.
Testing of semiconductor memory devices is generally performed through a test device to determine whether the memory core operates normally. A semiconductor memory device undergoing testing by a test device is referred to in industry as a DUT (Device Under Test). The test device applies a test item to a semiconductor memory device in order to perform a test operation of the semiconductor memory device. The test item provided in the semiconductor memory device is supplied to the memory core. The test item commonly includes a specific stress item and a pattern item. In addition, the test device provides power to the memory core when performing a testing operation.
The memory core includes a plurality of memory cells, and has a voltage range within which the memory cells operate under normal conditions. When the test device applies a specific stress item to the memory core, a voltage level that is higher than levels within the voltage range of normal operation is applied to the memory core.
When performing the test mode, the memory core responds to the specific stress item to test stability of the memory cells. In other words, in a case where the memory core receives as input a specific stress item, power is provided by the test device to each cell in response. It is possible to perform a stability test on the memory cells of the memory core by supplying a higher voltage level than the normal voltage range.
Specific stress items can include WBI (Wafer Burn In) and HVS (High Voltage Stress). When WBI and HVS items are supplied to the memory core, a voltage level that is not within the normal voltage range is supplied to the memory core. The WBI item further exposes the memory core to a temperature level that is out of range with respect to the normal temperature operation of the memory cells.
When the semiconductor memory device is undergoing a test operation, a pattern item is provided after a specific stress item is applied to the memory core. In a test device, in a case where a pattern item is provided to the memory core, a voltage level within the voltage range of normal operation of the memory cells is supplied to the memory core. Accordingly, when a pattern item is input, the memory core operates under normal voltage conditions. The pattern items can include, for example, data (pattern data, hereafter) and addresses for performing a programming operation in the memory cells of the memory core. The memory core programs pattern data to each memory cell designated by the addresses, and performs verification and reading operations for the programmed pattern data. Through these operations of the memory core, a determination is made as to whether the memory cells of the semiconductor memory device are operating normally.
The above-mentioned test operation is typically performed on a wafer consisting of a plurality of memory chips. In other words, the test device tests the plurality of memory chips on the wafer, where the plurality of memory chips are each a semiconductor memory device. The test device repeats testing until it is determined that all chips are performing normally. For example, when test mode of the test device is performed, some of the memory chips are tested and confirmed normal. However, test failure may occur in some of the memory chips due to external conditions such as contact defects resulting from dirt particles present between the test device and the memory chips. The memory chips in which a test failure has occurred may have had received an input of a specific stress item and may not have had received a pattern item, or, alternatively, the chips experiencing test failure may not have received either of the specific stress item or pattern item.
In this case, the test device performs a retest operation on all of the memory chips. However, if the retested memory chips have already received the specific stress item in the former test, and receive the specific stress item input a second time, or additional times, the memory cells may be rendered inoperative, or may undergo a change in performance characteristics, due to the subsequent application of the specific stress item.
For example, when test mode is performed, if a test failure occurs in some of the memory chips on the wafer, the test device performs a retest operation on all of the memory chips on the wafer. In other words, memory chips that have been tested and confirmed as operating normally in the former test, and memory chips that have received input of a specific stress item and have not received a pattern item, receive the specific stress item input a second time. Memory chips which have received specific stress item input a first time during the first test operation and then receive the specific stress item input again a second time during the second, retest, operation, are therefore subjected to the higher voltage level a second time.
If a memory chip that is determined to operate normally in the first test operation receives input of the specific stress item a second time in the retest operation, the application of the higher voltage a second time to the chip subjects the chip to the possibility of becoming damaged or undergoing a change in performance characteristics as a result of over-stress.